1. Field of the Invention
The present invention relates to a semiconductor device provided with an ESD (ElectroStatic Discharge) protection element.
2. Description of Related Art
An impedance matching technique by using a bridged T-coil is known (refer to, for example, Non-Patent Document 1: “40-Gb/s Amplifier and ESD Protection Circuit in 0.18-μm CMOS Technology”, Sherif Galal, Behzad Razavi, IEEE Journal of Solid-State Circuits VOL. 39, No. 12, pp. 2389-2396, December 2004). In a high-speed interface circuit provided with an ESD protection element, a parasitic capacitance of the ESD protection element and a parasitic capacitance of an input/output circuit affect impedance matching ability. In particular, impedance mismatch from a desired impedance (50Ω) is caused in a high-frequency region. The impedance matching by using the T-coil is a technique for preventing the impedance mismatch, namely cancelling the parasitic capacitance over a wide frequency range.
FIG. 1 is a circuit diagram showing a typical interface circuit provided with a T-coil and an ESD protection element. The interface circuit shown in FIG. 1 has a signal input pad 1, a signal line 2, a power supply line 3, a ground line 4, a tap interconnection 5, a T-coil section 10, a terminating resistor 12, an ESD protection element section 20 and a power ESD clamp circuit 30. The power supply line 3 supplies a power supply potential VDD. The ground line 4 supplies a ground potential GND.
The signal input pad 1 is used for inputting an external signal. The signal line 2 connected to the signal input pad 1 transmits the input signal. The T-coil section 10 has an inductor section 11 and a capacitor CB. The inductor section 11 has inductors L1 and L2. The capacitor CB is a bridging capacitor of the inductors L1 and L2. A parameter “k” is a coupling coefficient between the inductors L1 and L2. One end of the inductor L1 is connected to the signal line 2, and one end of the inductor L2 is connected to the terminating resistor 12. The other ends of the inductor L1 and the inductor L2 are connected to a center tap A. The tap interconnection 5 is connected to the center tap A. The tap interconnection 5 connects the T-coil section 10 and the ESD protection element section 20. One end of the terminating resistor 12 is connected to the inductor section 11, and the other end thereof is connected to the power supply line 3. It should be noted that the terminating resistor 12 may be connected to the ground line 4 instead of the power supply line 3.
The ESD protection element section 20 has an ESD protection element ESD_G (hereinafter referred to simply as ESD_G) and an ESD protection element ESD_V (hereinafter referred to simply as ESD_V). One end of the ESD_G is connected to the ground line 4 through an interconnection 21, and the other end thereof is connected to a connection point B. One end of the ESD_V is connected to the power supply line 3 through an interconnection 22, and the other end thereof is connected to the connection point B. The connection point B is further connected to the above-mentioned tap interconnection 5 and an internal circuit. The power ESD clamp circuit 30 is connected between the power supply line 3 and the ground line 4, and provides an ESD discharge path between the power supply line 3 and the ground line 4. Let r1, r2 and r3 be respective parasitic resistances of the tap interconnection 5, the interconnection 21 and the interconnection 22. It should be noted that a discharge path 100 shown in FIG. 1 corresponds to a case where ESD having a positive potential as compared with the ground potential GND is input to the signal input pad 1.
In the typical interface circuit, as shown in FIG. 1, the tap interconnection 5 connecting the T-coil section 10 to the ESD protection element section 20 is drawn only from a single point, the center tap A in the inductor section 11 (refer to, for example, Non-Patent Document 2: “Broadband ESD Protection Circuits in CMOS Technology”, Sherif Galal, Behzad Razavi, ISSCC 2003, Session 10, High Speed Building Blocks, Paper 10.5; and Non-Patent Document 3: “Novel T-Coil Structure and Implementation in a 6.4-Gb/s CMOS Receiver to Meet Return Loss Specifications”, Pillai Edward, Weiss Jonas, Electronic Components and Technology Conference 2007, Proceedings, 57th, pp. 147-153). The reason is to correctly reflect design parameters (L1, L2, CB and k in FIG. 1) of the T-coil section 10 in a layout of the T-coil section 10 based on the CMOS process. The layout of the T-coil section 10 is determined as follows. First, the design parameters of the T-coil section 10 are calculated. The design parameters are calculated based on a parasitic capacitance value C_total to be canceled (including ESD capacitance, gate capacitance of an input circuit and the like) and a desired impedance value Rs (e.g. 50Ω). Then, a metal interconnection of the inductor section 11 is laid-out in a spiral shape so as to achieve the calculated design parameters L1, L2, CB and k of the T-coil section 10. Here, a certain intermediate point of the inductor section 11 having the spiral shape is the center tap A, and the position of the center tap A is determined such that the calculated design parameters are achieved. Then, a node having the parasitic capacitance C_total is connected to the center tap A. In this manner, the impedance matching is achieved over a wide frequency range. To use the single center tap A for connecting the tap interconnection 5 may be important in correctly reflecting the design parameters of the T-coil section 10 in the layout of the T-coil section 10.
Equations for calculating the design parameters of the T-coil section 10 will be described below. FIG. 2 is a circuit diagram showing an interface circuit provided with a T-coil and a terminating resistor. In this case, the design parameters (inductances L1 and L2, bridging capacitance CB, and coupling coefficient k) of the T-coil can be expressed by the following Equation (1) (for example, refer to the above-mentioned Non-Patent Document 2).
                              [                      Equation            ⁢                                                  ⁢            1                    ]                ⁢                                                                                      {                                                                              L                  1                                =                                                      L                    2                                    =                                                                                                              C                          L                                                ⁢                                                  R                          T                          2                                                                    4                                        ⁢                                          (                                              1                        +                                                  1                                                      4                            ⁢                                                          ζ                              2                                                                                                                          )                                                                                                                                                                C                  B                                =                                                      C                    L                                                        16                    ⁢                                          ζ                      2                                                                                                                                              k                =                                                                            4                      ⁢                                              ζ                        2                                                              -                    1                                                                              4                      ⁢                                              ζ                        2                                                              +                    1                                                                                                          (        1        )            
In the Equation (I), CL is the parasitic capacitance value C_total to be canceled (including ESD capacitance, gate capacitance of an input circuit and the like), RT is the terminating resistance value, and ζ is a coefficient depending on characteristics. For example, in a case where there is a strong emphasis on the MFD (Maximally Flat group Delay), the following coefficient ζ is used.
                              [                      Equation            ⁢                                                  ⁢            2                    ]                ⁢                                                                                      ζ        =                              3                    2                                    (        2        )            
In this case, the design parameters in the above Equation (1) can be expressed by the following Equation (3).
                              [                      Equation            ⁢                                                  ⁢            3                    ]                ⁢                                                                                      {                                                                              C                  B                                =                                                      1                    12                                    ⁢                                      C                    L                                                                                                                                            L                  1                                =                                                      L                    2                                    =                                                            1                      3                                        ⁢                                          R                      T                      2                                        ⁢                                          C                      L                                                                                                                                              k                =                                  1                  2                                                                                        (        3        )            
For more details, please also refer to Non-Patent Document 4: “Handbook of Analog Circuit Design”, Dennis Feucht, San Diego, Calif., Academic, 1990. As described above, the design parameters of the T-coil can be expressed by using the parasitic capacitance CL, the terminating resistance value RT and the coefficient ζ. Let us consider a case where the parasitic capacitance CL=1 pF, the terminating resistor=50Ω and the coefficient ζ is as expressed by the above Equation (2). In this case, the bridging capacitance CB is calculated to be 83.3 fF, and the inductances L1 and L2 are calculated to be 0.833 nH. The layout of the inductor section 11 and the position of the center tap A are determined such that the calculated design parameters can be achieved. As a result, the parasitic capacitance of the ESD protection element and the parasitic capacitance of the input/output circuit can be canceled and the impedance matching is possible for a wide frequency range.
In the example shown in FIG. 1, a single-phase signal is input to an input circuit as the internal circuit connected to the T-coil section 10. The same applies to a case of an output circuit as the internal circuit connected to the T-coil section 10. Moreover, the same applies to a circuit that handles a differential signal instead of the single-phase signal. For example, an input circuit and an output circuit based on a differential configuration arc disclosed in the FIG. 10.5.3 and the FIG. 10.5.4 of the above-mentioned Non-Patent Document 2. The impedance matching and ESD tolerability arc achieved for a wide frequency range.
Semiconductor devices provided with an ESD protection circuit and an inductor are disclosed also in Japanese Patent Publication JP-H10-173133A and Japanese Patent Publication JP-2009-064923A.
The inventors of the present application have recognized the following points.
In the case of the configuration shown in FIG. 1, the CMOS internal circuit may be destroyed by a voltage increase due to an ESD current at a time when ESD is applied. Miniaturization of the CMOS process has been progressing, and a thickness of a metal interconnection particularly formed in the lower interconnect layer has been getting smaller. This causes increase in an interconnect resistance of the metal interconnection. For example, a sheet resistance of the metal interconnection is about 0.2 Ω/sq. In this case, the interconnect resistance of a metal interconnection with a width of 1 μm and a length of 10 μm is about 2Ω. Meanwhile, a gate breakdown voltage of a MOS transistor in the internal circuit in a case of 40 nm CMOS process is about 4 V. Therefore, if the ESD current whose magnitude is 3 A flows through the metal interconnection at a time when ESD is applied, the voltage increase of about 6 V is caused. Such the voltage stress far exceeds the gate breakdown voltage of 4 V and is large enough to destroy the CMOS internal circuit.
As shown in FIG. 1, the ESD_V connected to the power supply line 3 and the ESD_G connected to the ground line 4 are necessary in the ESD protection element section 20. However, the tap interconnection 5 from the T-coil section 10 to the ESD protection element section 20 is drawn only from the single point, the center tap A in the inductor section 11. Therefore, routing of a metal interconnection (tap interconnection 5) from the single center tap A to both of the ESD protection elements ESD_V and ESD_G is required. In this case, the metal interconnect path becomes complicated and the metal interconnect length becomes large. This causes increase in a parasitic resistance of the metal interconnection to each ESD protection element, which results in destruction of the CMOS internal circuit by the voltage increase due to the ESD current.
Moreover, in the case of the configuration shown in FIG. 1, a current density in the discharge path at the time when ESD is applied is high, which causes fusing of a metal interconnection. A thickness of a metal interconnection in a case of 40 nm CMOS process has been decreased to about 0.1 μm. Meanwhile, the magnitude of the ESD current flowing through the discharge path at the time when ESD is applied is not decreased. Therefore, the current density in the discharge path at the time when ESD is applied becomes higher, which causes fusing of the metal interconnection.
Furthermore, in the case of the configuration shown in FIG. 1, a circuit area is large. In the circuit shown in FIG. 1, a width of a metal interconnection of the discharge path 100 may be enlarged in order to reduce the current density and the interconnect resistance. However, as described above, the tap interconnection 5 from the T-coil section 10 to the ESD protection element section 20 is drawn only from the single point, the center tap A in the inductor section 11. Therefore, routing of a metal interconnection (tap interconnection 5) from the single center tap A to both of the ESD protection elements ESD_V and ESD_G is required. In this case, the metal interconnect path becomes complicated and the metal interconnect length becomes large. If the width of the metal interconnection is enlarged, further metal area needs to be ensured, which results in increase in an area of the ESD protection element section 20.
Moreover, the large metal area of the tap interconnection 5 to the two ESD protection elements ESD_V and ESD_G causes loss of the inductance values of the two inductors L1 and L2 of the T-coil section 10. Therefore, a larger inductor area is required in order to achieve the design parameters of the T-coil section 10, which results in increase in an area of the T-coil section 10. As described above, the miniaturization of the CMOS process is progressing, and an area of a CMOS circuit is getting smaller. However, the inductor of the T-coil section 10 and the ESD protection element section 20 hardly enjoy the benefit of the miniaturization of the CMOS process.